Serial Backplane IC

An off-the-shelf, CMOS-fabricated, quad-channel serial backplane interconnect IC with boundary scan is suitable for use in Gigabit Ethernet and Fibre Channel applications. As the first device in a planned family of serial backplane devices that test pin connectivity, the S2004 scans I/O signals with IEEE 1149.1 specification-compliant JTAG implementation. The device facilitates high-speed serial data transmission in a variety of applications, including Ethernet backbones, workstations, frame buffer, switched networks, data broadcast environments and proprietary extended backplanes. The instrument's highly flexible 0.98 to 1.3 GHz operating range makes it suitable for Gigabit Ethernet, Fibre Channel, serial backplanes and proprietary point-to-point links.

The quad-channel serial backplane interconnect provides four separate, full duplex, 1.25 Gbps transceivers that can be operated individually or locked together for an aggregate data capacity of up to 5 Gbps. Clock generation for the device is performed by a flexible on-chip transmit Phased Lock Loop (PLL) which synthesizes the high-speed clock from a 125 MHz (for 1.25 Gbps) or 62.5 MHz (for 625 Mbps rate) reference clock. Four receive PLLs synchronize directly to incoming signals, while simultaneously re-timing and regenerating the data stream. The device's transmitter and receiver each support differential PECL compatible I/O which minimizes crosstalk and maximizes data integrity.

AMCC (Applied Micro Circuits Corp.), 6290 Sequence Drive, San Diego, CA 92121-4358 Phone: 800-755-AMCC or 619-450-9333; Fax: 619-450-9885