Router Chip
It will help eliminate traffic jams by making it possible to design router systems that are faster and can be expanded to match the growth of traffic on the Internet. This same chip can also be used to boost the performance and provide scalability in products such as enterprise switches, optical switches, servers, telecommunications access equipment, cellular base stations, etc.
This chip works like a bullet train by packing data into a very high speed single lane connection that moves information ten times faster than parallel lanes. This "bullet train" approach is known as a serial backplane and it has the possibility of reaching speeds in the future up to a hundred times faster than existing parallel connections.
Each chip includes both a sophisticated transmitter and receiver that packs and unpacks 80 parallel lanes of data into eight lanes (i.e., bullet trains) each running up to 1.56 gigabits per second (i.e., 1.56 billion pieces of data per second).
It converts a 160 bit wide parallel backplane operating at 125 MHz into sixteen differential pair serial connections each operating up to 1.56 Gbps. The key functional blocks in the chip include a Clock Synthesizer, 8B/10B Encoders, Serializer/Deserializers (SerDes), Clock Recovery, Byte Aligners, 10B/8B Decoders and sixteen FIFOs (input & output). The device is manufactured using a standard CMOS process. The chip is designed for low power and consumes only 1.25Watts (typically) with a 2.5V supply.
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