OC-48 Transciever
Featuring a 4-bit LVDS data path at 622.08 Mbps, the S3457 offers a combination of a low jitter LVDS interface, low power, and extended temperature range. The device provides diagnostic loopback (transmitter to receiver) and line timing (receiver to transmitter) modes, which are capable of remaining active simultaneously. The S3457 also incorporates an internal FIFO (First In, First Out) to decouple transmit clocks, and an on-chip high frequency phase-locked loop (PLL) for clock generation. The PLL on-chip clock synthesis function enables the utilization of a slower external transmit clock reference. The reference clock features a frequency of 155.52 MHz, in support of existing clock schemes.
After receiving an OC-48 scrambled NRZ signal, the S3457 performs all necessary serial-to-parallel and parallel-to-serial conversions, including converting 4-bit parallel data into a bit-serial format at 2488.32 Mbps. These capabilities make the device ideal for SONET-based DWDM applications and can be used to implement the front end of SONET equipment consisting primarily of the serial transmit interface and the serial receive interface.
<%=company%>, 6290 Sequence Drive, San Diego, California 92121-4358; Phone: 1-800-755-AMCC.