OC-192/STM-64 line card chip set

Intel Corporationline card solution for OC-192/STM-64 SONET/SDH transmissions systems begins with the introduction of GD30001, a 10Gbps Forward Error Correction single chip transceiver and GD32003, OC-192/STM-64 Section and Line Termination single chip transceiver. The chip set also includes GD19906, a Transimpedance Amplifier; GD19902, an Automatic Gain Control Amplifier; GD16584, 9.95 Gbps CDR with 1:16 deserializer; GD16588, 10.7 Gbps CDR with 1:16 deserializer; GD16585, 9.95 Gbps 16:1 serializer with CMU; GD16589, 10.7 Gbps 16:1 serializer with CMU and GD19901, a Laser Modulator Driver.

GD30001 Forward Error Correction (FEC) transceiver:

This is a single chip 10Gbps Forward Error Correction device that enables system designers to enhance the performance of their optical transmission system by improving the signal-to-noise ratio (SNR) of their transmission links. It utilizes a Reed-Solomon based (255,239) error correction code according to ITU-T G.975. GD30001 offers communications channels of up to 35 Mbps for Operation, Administration and Maintenance (OAM) of the optical network. It is equipped with a complete statistics section for reporting error rates and correction statistics. It may be operated as FEC transmitter wrapping the payload data stream, as FEC receiver unwrapping received data, as FEC transceiver or as error correcting regenerator. It is designed for DWDM applications and is optimized for low power and reduced board space.

GD30001 has a 16-bit LVDS I/O interface at the line side running at 666 MHz. The system side interface has a similar 16-bit LVDS I/O interface running at 622 MHz. It offers various loop back modes and can be controlled by an optional microprocessor via an 8-bit microprocessor interface. The IC is manufactured in a 0.18µ CMOS technology and is packaged in a 576-pin BGA package.

GD32003 Section and Line Termination transceiver:

The GD32003 is a complete Section and Line termination transceiver operating at OC-192/STM-64 speed. It aggregates four frequency locked STM-16/OC-48 lines into a single OC-192/STM-64 connection. It features two on-chip STS-1 level Time Slot Interchange switches.

GD32003 features full section and line overhead termination with both microprocessor and external access to overhead bytes. It performs performance monitoring including error statistics on all line and system side interfaces. The device interfaces to the 10 Gbit/s line at 622 MHz with 16-bit LVDS. The system side interface consists of either four STM-16/OC-48 4-bit 622 MHz LVDS interfaces or a single 10 Gbps 16-bit 622 MHz interface. The STM-16/OC-48 interfaces are equipped with a skew compensating FIFO, which tolerates up to 500 ns of skew between the individual STM-16/OC-48 inputs. This also allows the design of transmission systems to carry OC-192/STM-64 payload over four STM-16/OC-48 optical transmission lines. GD32003 is manufactured in a 0.18µ CMOS technology and packaged in a 576-pin BGA package.

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