Dual-Port Gigabit Ethernet Transceiver
This third-generation, full-feature physical layer transceiver with integrated PMD sub layers supports 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Based on a field proven architecture, it is manufactured on the company's 0.18-micron CMOS technology, providing a high level of integration at a low power consumption.
The transceiver provides PHY level cyclical redundancy checking (CRC), on received packets and PHY level CRC generation for test mode transmit packets. It supports JPAG, and Auto media dependent interface crossover (Auto-X) that automatically detects and corrects wiring mishandling such as swapped wires in addition it also provides for and automatically corrects reversed polarity.
The device is designed for easy implementation of 10/100/1000 Mbps Ethernet LAN Switches. Each of the two ports interfaces directly to Twisted Pair media via an external transformer. It interfaces directly to the media access controller (MAC) layer through the IEEE 802.3u Standard Media Independent Interface (MII) of the IEEE 802.3u Gigabit Media Independent Interface (GMII). The transceiver also supports the reduced pin count serial GMII (SGMII) interface with eight pins per port.
Features:
Single Quad TX-Transformer interface for all speeds
Adaptive equalization and Baseline Wander compensation
IEEE 802.3u Auto-Negotiation and parallel detection
3.3 v/1.8 v MAC interfaces
LED support
Management register set
Acceptance of 125 MHz or 25 MHz clock input
National Semiconductor Corporation, 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, CA 95052-8090. Tel: 408-721-5000; Fax: 800-737-7018.