Communications Processor

CALISTO is a single-chip communications processor for carrier-class voice gateways, soft switches and remote access concentrators/remote access servers (RAC/RAS). The patent-protected signal processing architecture called Configurable Algorithm-adaptive Instruction Set Topology is implemented within the chip. This architecture provides greater signal processing throughput in an efficient silicon implementation. The device provides over 3.3 GMACs of signal processing horsepower and 1.4Mbytes of high-speed memory which translates into 240 packet telephony channels on a single chip. The chip replaces up to 10 traditional DSP discrete components, enabling the convergence of voice and data services over a unified data network with a high density of voice channels per square inch and per watt.

The chip has been designed for the complex packet processing, signal processing, and high-speed memory requirements for next generation carrier and broadband access networks. It manages the compute-intensive tasks including: echo cancellation, voice/fax and data modem signal processing, packetization, cellification, delay equalization and telephony protocols within packet telephony applications such as carrier gateways, broadband access gateways and remote access concentrators.

The adaptive instruction set architecture, along with the C-compiler and Integrated Development Environment (IDE), shortens the product development cycle. The chip's real-time operating system (RTOS) enables voice and data Service Providers to provision it for Any Service Any Port (ASAP) configurations ranging from 240 channels of carrier class G.711 packet telephony to 60 channels of full Universal Port.

Systems using the chip achieve over 400 channels per square inch and deliver a power consumption of less than 10 milliwatts per channel. The chip's 239-pin BGA has been designed for maximum density placements of multiprocessor configurations. The device is augmented by a comprehensive IDE that includes an Optimizing C Compiler, RTOS and Multi-processor Debug Environment. The IDE is supported by a quad Evaluation Module (EVM) or a software simulator.

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