CDR Unit
The high input sensitivity of the unit, along with its ability to retime data at the output, provides design engineers a solution for maximizing data coherency. Data that is propagated over long lengths of fiber or traversed through multiple stages of a switch fabric results in signal degradation. The CDR maintains data integrity by reshaping the signal using its recovered, low jitter clock.
The high-speed clock and data outputs support multiple I/O types adding flexibility for the design engineer. The outputs can be terminated as LVDS differential outputs by placing a 100-ohm register between the differential signals, or they can be terminated as LVPECL differential outputs. The unit isackaged in a board space saving 20 pin TSSOP.
Vitesse Semiconductor, 741 Calle Plano, Camarillo, CA 93012 Phone: 805-388-3700 Fax: 805-987-5896