ATM Switch Chipset
The non-blocking ATM architecture is scalable from 622 megabits/second (Mbps) to 20 Gbps. It supports full duplex per-connection speeds ranging from 37 Kbps to 622 Mbps, with capability to store up to 64 K cells per OC-12 (622 Mbps) link at external buffer. The initial release will support 16K virtual connections (VC) per OC-12 link, increasing to 64K VCs by year-end. A UTOPIA (Universal Test & Operations PHY Interface for ATM) Level II interface operating at 50 MHz provides connectivity for up to 31 physical ports. A high level of integration provides a robust feature set fully compliant with ATM Forum User Network Interface (UNI) 3.1, 4.0 and Traffic Management (TM) 4.0.
The chipset features a broad range of traffic congestion and switch management functions to maintain optimum performance under varying conditions. Five quality of service (QoS) classes are supported: constant bit-rate (CBR), real-time variable bit-rate (rt-VBR), non-real-time variable bit-rate (nrt-VBR), available bit-rate (ABR) and unspecified bit-rate (UBR). For ABR congestion management, one of three internal processors handles ABR load information and RM (Resource Management) cells. Backward RM cells (BECN: Backward Explicit Congestion Notification) may be generated to inform the ABR source of congestion conditions in the switch. The chipset also incorporates functionality for 32 shapers, flow control, scheduling, per-VC queuing, and three modes of high-performance multicasting.
Toshiba's chipset is comprised of three devices; the Switch Access with Multiplexer (SAM), the Switch Element (SE) and the Distributor/Arbiter (DA), all of which can be combined in various configurations to achieve different levels of performance.
Toshiba America Electronic Components, 9775 Toledo Way, Irvine, CA 92618-1811 Phone: 949-455-2000